功率电感生产厂家
联系我们
热门搜索
点击排行
推荐阅读
猜猜你喜欢的
技术知识 您所在的位置: 首页 > 技术知识

Altera StratixIV 100G开发方案介绍

来源:    作者:    发布时间:2015-10-09 22:34:40    浏览量:

Altera公司的Stratix IV 40nm FPGA包括Stratix IV E, Stratix IV GX和Stratix IV GT三个系列, 具有最高的密度(680K 逻辑单元(LE),22.4 Mbits 嵌入式存储器和1,360个18 x 18 乘法器),最佳的性能以及最低的功耗, 系统带宽(8.5 Gbps的48 个高速收发器,以及 1,067 Mbps (533 MHz) DDR3存储器接口)达到了前所未有的水平,并具有优异的信号完整性, 非常适合无线通信,固网,军事,广播等其他最终市场中的高端数字应用。本文介绍了Stratix® IV FPGA主要特性, Stratix IV GT器件框图,以及采用EP4S100G5F45I1 Stratix IV GT FPGA器件的Stratix IV GT 100G开发大功率电感贴片电感器板主要特性,方框图,详细电路图和材料清单.

Altera® Stratix® IV FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. Stratix IV FPGAs are based on the Taiwan Semiconductor Manufacturing Company (TSMC) 40-nm process technology and surpass all other hi电感生产厂家gh-end FPGAs, with the highest logic density, most transceivers, and lowest power requirements.

The Stratix IV device family contai一体电感ns three optimized variants to meet different application requirements:

■ Stratix IV E (Enhanced) FPGAs—up to 813,050 logic elements (LEs), 33,294 kilobits
(Kb) RAM, and 1,288 18 x 18 bit multipliers

■ Stratix IV GX transceiver FPGAs—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers, and 48 full-duplex clock data recovery (CDR)-based transceivers at up to 8.5 Gbps

■扁平型电感 Stratix IV GT—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers, and 48 full-duplex CDR-based transceivers at up to 11.3 Gbps

Stratix® IV FPGA主要特性:

The following list summarizes the Stratix IV device family features:

■ Up to 48 full-duplex CDR-based transceivers in Stratix IV GX and GT devices supporting data rates up to 8.5 Gbps and 11.3 Gbps, respectively

■ Dedicated circuitry to support physical layer functionality for popular serial protocols, such as PCI Express (PCIe) (PIPE) Gen1 and Gen2, Gbps Ethernet (GbE), Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, and Interlaken

■ Complete PCIe protocol solution with embedded PCIe hard IP blocks that implement PHY-MAC layer, Data Link layer, and Transaction layer functionality

■ Programmable transmitter pre-emphasis and receiver equalization circuitry to compensate for frequency-dependent losses in the physical medium

■ Typical physical medium attachment (PMA) power consumption of 100 mW at 3.125 Gbps and 135 mW at 6.375 Gbps per channel

■ 72,600 to 813,050 equivalent LEs per device

■ 7,370 to 33,294 Kb of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port 绕线电感memory and FIFO buffers

■ High-speed digital signal processing (DSP) blocks configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers at up to 600 MHz

■ Up to 16 global clocks (GCLK), 88 regional clocks (RCLK), and 132 periphery clocks (PCLK) per device

■ Programmable power technology that minimizes power while maximizing device performance

■ Up to 1,120 user I/O pins arranged in 24 modular I/O banks that support a wide range of single-ended and differential I/O standards

■ Support for high-speed external memory interfaces including DDR, DDR2, DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular I/O banks

■ High-speed LVDS I/O support with serializer/deserializer (SERDES), dynamic phase alignment (DPA), and soft-CDR circuitry at data rates up to 1.6 Gbps

■ Support for source-synchronous bus standards, including SGMII, GbE, SPI-4 Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1

■ Pinouts for Stratix IV E devices designed to allow migration of designs from Stratix III to Stratix IV E with minimal PCB impact

Stratix IV GT Devices

Stratix IV GT devices provide up to 48 CDR-based transceiver channels per device:

■ Thirty-two out of the 48 transceiver channels have dedicated PCS and PMA circuitry and support data rates between 600 Mbps and 11.3 Gbps

■ The remaining 16 transceiver channels have dedicated PMA-only circuitry and support data rates between 600 Mbps and 6.5 Gbps

49.gif49.gif
图1. Stratix IV GT器件框图

Stratix IV GT器件主要特性:

50.gif

  • 采用Mini-SPM设计高压侧栅极驱动电路 引言Mini-SPM系列产品,为低功率 (100W ~ 2.2kW) 电机驱动电路提供高效率、高可靠性和设计简便的方案。Mini-SPM采用内置高压驱动IC (HVIC) 作为栅极驱动电路,使设计更

  • 多少W的电源需要PFC呢?适配器和LED灯对PFC的要求是怎样定义的呢?对应的功率 是多少呢?以前是大于75W,上次听讲座好像现在大于45W就要带PFC功能了。
    见得比较多的,65W以上的适配器都有PFC,


    灯就没这

  • kis3r33模块的双路隔离输出请教

    坛里有用过KIS3r33模块实现两路隔离输出的大神么?我最近在做这个,原理是将模块上面的电感拆点,换成高频磁环,铁硅铝的磁环,可是在实验的时候发现:


    1.当输入5V的

  •